Can slow power-down or repeated power cycling damage the RAK3112 even when VDD remains below approximately 3.6 V?

Hello,

I am investigating a recurring failure involving RAK3112 modules during power-up / power-down events.

So far, three RAK3112 modules have failed in the context of power cycling . In the latest case, the module stopped working while I was repeatedly turning the bench power supply on and off during measurements of the power-down behavior.

The board uses a hold-up power system . The RAK3112 is powered from a 3.3 V rail generated by a TRACO TSR1-2433E, while a capacitor bank maintains the upstream supply for some time after the main input power is removed.

Because of this architecture, I initially suspected that some external GPIO could remain powered while the RAK3112 VDD was already falling, potentially creating a voltage difference between a GPIO and VDD.

However, we have already checked this behavior with an oscilloscope and have not found any GPIO remaining above VDD while the module supply falls toward 0 V. In other words, so far we have not observed a clear back-powering condition through the GPIOs.

I also suspected my bench power supply because all three failures occurred around power-up / power-down events.

I therefore measured the RAK3112 supply directly at the module pins using a Rigol DHO814 oscilloscope with a ground spring to minimize measurement artifacts.

During multiple power-on and power-off tests, the highest transient I was able to capture on the RAK3112 VDD rail was approximately:

  • Nominal VDD: 3.3 V
  • Maximum observed transient: approximately 3.55–3.65 V
  • Transient duration: in the microsecond range

I have not been able to capture any substantially higher voltage directly at the RAK3112 VDD pins.

The most recent failed module was not under any unusual RF load when the failure happened. The unit was operating as a slave, essentially remaining in RX, and the only peripheral connected was a PN532 through an I²C level-shifting circuit.

After the failure, the RAK3112 also disappeared from USB, so this does not appear to be only an RF/LoRa failure.

My main questions are:

  1. Can repeated power cycling or a slow VDD decay damage the RAK3112 even if the measured VDD peak remains around 3.65 V?
  2. Are there any specific requirements for the RAK3112 regarding:
  • VDD rise time;
  • VDD fall time;
  • minimum VDD that must be reached before power is reapplied;
  • minimum OFF time between power cycles?
  1. Is there any potentially unsafe operating region when VDD decreases slowly through the brownout / undervoltage region?
  2. Is 3.65 V for a few microseconds considered potentially destructive for the RAK3112, or would you expect the module to tolerate such a short transient?
  3. Are there absolute maximum ratings or power sequencing requirements for the RAK3112 that are not currently included in the public datasheet?

At this point, the strongest correlation I have is between the module failures and power-up / power-down events, but I have not yet been able to capture an electrical transient that clearly explains the failures.

Any guidance regarding the expected behavior of the RAK3112 during slow power-down or rapid/repeated power cycling would be very helpful.

Hi Paulo,

There is no known issue on RAK3112 as related to power cycle.

As for operating 3.65v, that is already above its operating max voltage so that could possibly causes the issue.

As for rise/fall time of VDD, there is no specific requirement. ESP32 only requirest correct rise/fall time on enable pin to ensure that it will boot correctly.

My suggestion is to bypass the powersource you have and try to use your lab power supply temporarily so you can have a fix 3.3v and operate without specifications. This way, we can isolate the issue if it is caused by the 3.65v spikes.