RAK3272S: which board revision ships, and conflicting J4 pin 1/2 documentation

Two questions about the RAK3272S Breakout Board, 9xx MHz.

  1. The datasheet says the J4 pin table applies to VerC, and that on VerB
    pin 9 is PA8 rather than 3V3. Which revision ships today?

  2. The datasheet lists J4 pin 1 as I2C2_SDA (PA11) and pin 2 as I2C2_SCL
    (PA12), but the quickstart’s Digital I/O table lists J4 pin 1 as PA8
    and pin 2 as PA9. Which is correct for the current board?

And a design question: my application needs one ADC input and one GPIO
with external-interrupt capability from the module, and neither appears
on J4 or J5. Is there any pad, test point, or castellation on the
RAK3272S that reaches an unbroken-out module pin such as PA10 or PA1, or
is a custom carrier board the only route?

Welcome to the forum @Wrjackson

  1. Only VerC is shipped.

  2. The pins are multi-use GPIO’s. Both names are correct. When using RUI3 API, you can choose whether you want to use them as GPIO or for the I2C bus

There are no pads or test points on the breakout board. Only signals on the pin headers are accessible.

For GPIO with interrupt capability you can use any GPIO.
For analog input, PA11 and PA12 can be used as analog input and they are available on the pin headers. To use them, don’t activate the I2C bus assigned to them and instead declare them as analog inputs.

For references from the STM32WLE5CC datasheet, the following GPIO’s support analog input:
PA10
PA11
PA12
PA13
PA14
PA15

PB1
PB2
PB3
PB4
PB13
PB14