We have a couple of RAK4631 modules that we are developing a custom board for.
The firmware should be Arduino BSP.
OS is Windows 11 or MacOS X. I have tried both the Arduino IDE toolchain as well as PlatformIO.
We soldered a pinheader to the five connectors (3V3, SWDIO, SWCLK, GND, RESET) directly on the board. We tried a Segger J-Link and two ST-Links, but no SWD connection was possible.
Regarding the pinout, I followed WisBlock/bootloader/RAK4630 at master · RAKWireless/WisBlock · GitHub (note though: VCC is 5V on the J-Link, therefore I did not use that connection and instead connected an external 3V3 power supply.
J-Link>Device nRF52840_xxAA
J-Link>Speed 1000
Selecting 1000 kHz as target interface speed
J-Link>Connect
Please specify target interface:
J) JTAG (Default)
S) SWD
T) cJTAG
TIF>S
Device “NRF52840_XXAA” selected.
Connecting to target via SWD
InitTarget() start
InitTarget() end - Took 103ms
Found SW-DP with ID 0x2BA01477
DPIDR: 0x2BA01477
CoreSight SoC-400 or earlier
Scanning AP map to find all available APs
AP[2]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x24770011, ADDR: 0x00000000)
AP[1]: JTAG-AP (IDR: 0x02880000, ADDR: 0x01000000)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Found Cortex-M4 r0p1, Little endian.
FPUnit: 6 code (BP) slots and 2 literal slots
CoreSight components:
ROMTbl[0] @ E00FF000
[0][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7
[0][1]: E0001000 CID B105E00D PID 003BB002 DWT
[0][2]: E0002000 CID B105E00D PID 002BB003 FPB
[0][3]: E0000000 CID B105E00D PID 003BB001 ITM
[0][4]: E0040000 CID B105900D PID 000BB9A1 TPIU
[0][5]: E0041000 CID B105900D PID 000BB925 ETM
Memory zones:
Zone: “Default” Description: Default access mode
Cortex-M4 identified.
J-Link>Erase
No address range specified, ‘Erase Chip’ will be executed
‘erase’: Performing implicit reset & halt of MCU.
Reset type: NORMAL (J-Link Reset Strategies - SEGGER Knowledge Base)
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
Reset: SYSRESETREQ has confused core.
Found SW-DP with ID 0x2BA01477
DPIDR: 0x2BA01477
CoreSight SoC-400 or earlier
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Found Cortex-M4 r0p1, Little endian.
Reset: Using fallback: VECTRESET.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.VECTRESET.
Erasing device…
J-Link: Flash download: Only internal flash banks will be erased.
To enable erasing of other flash banks like QSPI or CFI, it needs to be enabled via > “exec EnableEraseAllFlashBanks”
J-Link: Flash download: Total time needed: 0.348s (Prepare: 0.279s, Compare: > 0.000s, Erase: 0.068s, Program: 0.000s, Verify: 0.000s, Restore: 0.000s)
ERROR: Erase returned with error code -5.
All similar attempts with i.e. nrfjprog --log --family nRF52 --eraseall failed.
What are we doing wrong?