Hello RAK technical team,
Could you review these interfaces before we assemble an academic prototype? We use three exact RAK3172-9-SM-I modules on node cores: two at 3.3 V and one at 3.4 V, each from TPS63900. A separate central uses a complete external RAK3272S breakout. Initial testing is in a 20–40 °C laboratory. No hardware tests have been completed.
Node connections
- Pin24=regulated VDD; pins11/17/18/23/28=GND. Local bypass is 100 nF plus 10 µF (GRM21BR71A106KE51L); the converter has 47 µF on the same rail.
- RST pin22: 10 kohm to VDD and 100 nF to GND. BOOT0 pin21: 100 kohm to GND.
- Our service header: 1 GND; 2 target-voltage reference only; 3 SWDIO→RAK7/PA13; 4 SWCLK→RAK8/PA14; 5 RST→RAK22; 6 UART2_RX→RAK1/PA3; 7 UART2_TX→RAK2/PA2; 8 BOOT0→RAK21. The programmer does not power the target.
- For this -I antenna-connector variant, pin12/RF and pin27/PB12 are unconnected. We use the module antenna connector; there is no carrier RF feed or matching network.
Central
A TPS7A0233DBVR supplies RADIO_3V3 with 10 µF + 2×100 nF on the carrier. Connections to RAK3272S: J5-9/3V3, J5-7/GND, J4-8/UART2_RX and J4-7/UART2_TX. UART is crossed through TXU0202, with 10 kohm radio-RX pull-up and OE-to-GND inhibit jumper. A single USB source feeds the carrier through an external STPS1L60A; no programmer supply is connected.
Questions
- Are the supply/bypass, reset/BOOT and programming connections suitable for this exact module, including 3.4 V operation? What additional ramp/reset or unpowered-interface precautions are required?
- Can you provide a conservative maximum input-capacitance envelope for the complete RAK3272S, including onboard and internal module capacitance, over startup (0–3.6 V) and 20–40 °C, with revision/tolerance/bias information? Our current LDO allows total effective COUT ≤22 µF. The breakout schematic shows 10 µF + 100 nF, giving 20.3 µF nominal including our carrier, before tolerance/internal capacitance. A TLV75533PDBVR alternative is only a review candidate, not adopted.
- What peak current/transient envelope should we allow for 915 MHz LoRa P2P, including +20 dBm TX, startup and retries? We have not treated the published 87 mA at 868 MHz as a guaranteed maximum.
- Please confirm pin12-NC and any grounding/under-module/connector clearance restrictions for the -I version. I can provide a minimal footprint/mask image if needed.
Please identify corrections, assumptions and remaining first-board tests, rather than certifying the whole system. No paid service or hardware change is authorized. Thank you.
